Die stacking may be used in three-dimensional flip-chip integration, and typically involves mounting one or more chips on another chip in a single semiconductor package. This process can increase the amount of circuitry that can be housed within a package of a given size, and thus can reduce the area utilized on a printed circuit board. Die stacking may also simplify the assembly of printed circuit boards since multiple dies may be attached to a printed circuit board in a single operation. Die stacking also has the potential to improve the electrical performance of devices in which it is used since the interconnections between elements on each of the stacked dies may be shorter than the interconnections that would be required to connect the die elements on a planar surface. This can result in faster signal propagation and may also reduce cross-talk.
Connections may be formed between circuits residing on stacked dies by using Through Silicon Vias (TSV's). As the name suggest, a TSV is a conductive via formed through a layer of silicon that provides electrical connections between circuits on both sides of the via. A conventional die stacking arrangement using TSV's is illustrated in FIG. 1. Here, a first die 100 is connected to a second die 112 using a TSV 106 and a microbump 110. The first die 100 may include a substrate 102 on which conventional layers of circuitry are formed and an outer metal layer 104. The through silicon via 106 may be formed in the substrate 102 by conventional processes, which can involve thinning the substrate to expose an end of the TSV 106, and a redistribution layer 108 may be added to the side of the substrate opposite the conventional layers of circuitry. The microbump 110 may be formed on the redistribution layer 108 to provide a mechanical/electrical connection to the TSV 106. A second die 112 that can be stacked on the first die 100 may include a substrate 114, an outer metal layer 116, and a microbump 118. Electrical connections are formed between the first die 100 and the second die 112 by inverting the second die 112 and connecting the microbump 118 on the second die 112 with the microbump 110 on the first die 100.
The TSV and the microbumps may form a connection set having two ports (not shown) which carry the signal bi-directionally between the circuits on the two dies 100 and 112. This arrangement may provide a satisfactory connection between stacked dies for signals having lower frequencies. However, at higher frequencies, such as, for example, RF frequencies over GHz, the connection set may introduce a parasitic reactance into the signal path. This parasitic reactance may be capacitive, and can adversely affect the performance of the circuitry associated with die 100 and/or die 112.
Accordingly, there is a need for improved coupling techniques used in three dimensional flip chip assemblies, which do not introduce parasitic impedances that may affect the performance of integrated circuits.